Code converter system and method

ABSTRACT

A system and method for converting binary coded decimal numbers to binary and for converting binary to binary coded decimal. Read only memories include a programmed mapping between the binary and binary coded decimal codes. Input to the read only memory in one code is converted to an output in the other code. The outputs from the read only memories are summed to produce the desired result.

CODE CONVERTER SYSTEM AND METHOD Inventors: Edmund T. Burke, West Long Beach; Donald F. Kennedy, South Toms River, both of NJ.

Assignee: Electronic Associates, Inc., West Long Branch, NJ.

Filed: May 7, 1973 Appl. No.: 357,624

US. Cl. 340/347 DD; 235/155 Int. Cl. H03k 13/24 Field of Search 235/155; 340/347 DD References Cited UNITED STATES PATENTS 5/1962 Couleur 235/155 May 6,1975

3,652,840 3/1972 Lanning 235/155 3,652,841 3/1972 Lanning 235/155 3,700,872 /1972 May 235/155 Primary Examiner-Malcolm A. Morrison Assistant Examiner-Vincent J. Sunderdick [57] ABSTRACT A system and method for converting binary coded decimal numbers to binary and for converting binary to binary coded decimal. Read only memories include 1 Claim, 3 Drawing Figures 8M! g g PU}? SQ a/zv :60 g g 2/0 400 00 fi so "a g g PU}? PU/PI no ADD Qg r;

Q 7: r: w

.950 g g I 400 Q u L U I /20 30 /40 SIGN PATENIEU 1m ems 3.882.483

SHEET 2 Pmmmm 5:975 3,882,483

SHEET a/A/Anr wpur AVG/P0 0 2 3 4 0 l3 /4 ROM A (50. 00) ROM 0 (/00 ADDRESS 4000550 05678 'OQ/O/I/Z ROM .9 (70. 00) R0 0 (.90)

ADDRESS 40005.9:

1 CODE CONVERTER SYSTEM AND METHOD BACKGROUND OF THE INVENTION and binary coded decimal are known in the art. One

Another prior technique utilized in the art is a denominated Couleurs technique. This is a serial approach to the code conversion process, thus resulting in a comparatively slow running time. In order to fabricate a parallel converter, complex additional circuitry is required for fast, efficient operation. However, even after being modified, the efficiency of this approach breaks down for binary words of length greater than seven bits.

Other methods of code conversion such as, (1) divide by (where successive division by 10 converts binary images into BCD) and (2) multiply by 10 (with each product generating a BCD digit), are known in the art. However, such conversion systems and methods produce slow running times.

Other prior art utilize parallel conversion methods which are based upon logic elements operating on all bits ofa word to be converted simultaneously. In some of these systems read only memory units are employed. However, in such units, where a negative number is entered, it is initially one complemented. Then while it is still a binary number (assuming a conversion from binary to BCD), a least significant bit is added to form the twos complement is manipulated in the conversion. Thus the ripple through time for a negative number would exceed that of a positive number. This provides for longer running time in the conversion technique than that which would be seen if both negative and positive numbers were treated in the same way.

I SUMMARY OF THE INVENTION signals from the logic circuits for producing the digital output signal in one of the codes.

2, BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a functional schematic block diagram of the binary to binary coded decimal converter;

FIG. 2 is a functional schematic block diagram of the binary coded decimal to binary converter; and,

FIG. 3 is a block diagram showing bit information placed in read only memory addresses.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the invention, FIGS. 1 and 2 there are shown the functional block diagrams for a system for converting digital input signals to digital output signals between binary coded decimal and binary code signals. Conversion system 2, shown in FIG. 1 is used for converting binary to binary coded decimal signals. Conversion system 4, shown in FIG. 2 is used for converting binary coded decimal signals to binary. Number converters 2 and 4 basically use the same principles of operation to convert the signals between binary and binary coded decimal (BCD). In general, an input number is applied to converters 2 and 4 in one of the codes. The input number is broken apart into separatedecades of information. Specific portions of the input numher are used as address lines for read only memory elements. The read only memory units convert from one code to another and the outputs are then summed together and passed through an output driver stage.

Binary to BCD converter 2, is shown in FIG. 1, where a binary number is inserted to quad latch mechanisms 10, 20, 30 and 40 through input line 8. Converter 2 is a ripple through parallel hardware number converter, which accepts a 14 bit plus sign fractional binary number input and produces a four BCD digit plus a sign output. Quad latch mechanisms 10, 20, 30 and 40 are standard elements utilized as input registers having an EAI (Electronic Associates, Inc.) part number 592.0168-0. The inputs to these elements are labeled bits 0 through 14. Bit 0 is the sign bit and is entered through quad latch 40. The binary input word is shown in FIG. 3.

The output of quad latch 10 are bits 1, 2, 3 and 4 which are applied to read only memories 50 and 60 (ROM AU and ROM AL). Additionally, sign bit 0 is applied to ROM AU and ROM AL 50, 60 through quad latch 40. Similarly, bits 0, 5, 6, 7 and 8 are applied to ROMs BU and BL, 70, from quad latch mechanisms 20 and 40. Bits 0, 9, 10, 11 and 12 are applied to ROM C, and finally bits 0, 13, 14 to ROM D, as is shown.

The address lines for the bit signals applied to ele-' TRUTH TABLE BIN TO BCD CONVERTER 2 80 60', 70," 80;, 90 and 100 have output lines labeled Tl-l (thousands)', -H (hundreds'),'TE (tens) and'U (units) rehpi'eisentingtho's'e portions of the contribution to the v toutpjutjfriom the associated incoming ROM bitsQ u Qnth'dirtphtsbf elements 50, 60, 70, 80 and 90 are 15011111) tsistel' elements (FUR) 160, l70'and 240. Al- 1 "though-not"critical to the inventive concept, these resister elementspi'ovide collector loads for the output. "011113 111 5 1; from elements 60 and 100 are summed 1 ibgemer in binary adder 120. The output of adder 120 is appliedfto B CD adder-l30 and summed with the units TRUTH TABLE Continued 3 a g BIN TO 13c1) CONVERTER2 1 50,60 1 r 70,80 90 100 ROM A-- ROMB ROMC ROMD ADR OUT-PUT ADR OUTPUT. ADR H'OUTPUT ADR OUTPUT 01234 u' '1.- v0567s u 1,. 09101112 I u L 01314 n 1.

00011 @1875"; 00011 0117 00 ,0 1 1 0007 0 1 1 0002 ,00100 2500 400100 0156 00 1, 0 0 0010 1 0 0 0002 00101 v3125 -00101- 0195 00 1 ,0 1 0012 1 0 1 0002 00110 3750 '0011' 0 02 34 00 1 1 0 0015 1'1 0 0001 00111 ".4375 -00111 0273 1 00 1. 1 1 0017 1 1,1 0001 01000 5000 01000 03 12 01 0 0 0 00 01001 5625 01001 0352 01 0 0 1- 0022- 01010 36250 01010 50391 01 0 1 0 0024 01011 .6875 010111 0430 01 01 1 0027 01100 75 00 01100 '04 69 01 1 0 0 00 29 (01101 12125 01101 0508 01 1 0 1 0032 0111018750 01110 .0547 I 01.1 1 0. 0034 01111-- 9375 01111 0586 01 1 1 1 0037 vv10000 1 9375, "10000 0586 .10 0 0 0 ;00 37 =10001v "8750 1 10001 05 47 10 0 ,0 v1 00 34 10010 s125 '10010 a 05 0s 10 0 1 0 00 32 10011 175 00 ,10011 1 04 09 10 0 1 .1 0029 10100; 618 75 a 10100 0430 10 1 0 0 0027 10101- 6 2'50 10101 03 91 10 1 0-1 V 0024 1 10110 .5625 10110- 03 52 10 a 1, 1 0 00 22 10111 1; 5000 10111 0312 101' 1 1 0020 11000 4375 11000 0273 171 0 0 0 00172 11001 "-37-50 --j11001 0234 11 0 0 1 0015 11010 3125 11010. 0195 11 0 1 0 0012 1 10115 :00 11011 0150 11 0 1 1 0010 1110031875 11100 0117 11.10 0 0007 11101 -1250; 11101 7 0078 11,1 0 1 0005 1 11110 -0625 11110 0039 11 1 1 0- 0002 1 11111 0000 11 1 1 1 0000 output of;00,"25 ,50, or depending on the value of 1 the input 11113 0 354. It is therefore to be understood th'atRQM Alt-5,560 may be eliminated and combina tio'nal logic inserted invits place. Each of elements 50,

ii The'tensoutput 110 ROM '0, 90, and ROM BL,

have been taken from ROM elements 50,560, 70, 80, and and summed together to achieve an output BCD number from elements 140, 190,. 220 and 2501 The thousands digit i s'read from adder' 250, the hun 1 i ,dreds digit from adder 220; the tens digitfroin element 190 and the units digit from adder 140. The resulting numbers are then fed into standard output drivers 2 00, 230 and 260 as shown in FIG. 1. The Sign bit (bit 0) is carried from quad latch 40 to output driver 1 10 and is presented to the output to drive the-signof an in dicator. 1.

ln the truth table (BIN to BCD Converte'r) the first sixteen binary entries for ROMs 50, 6 0 70, 80 and 90 are added together in BOD adder The output of adderi8 0 is ffed directly into adder element 190, where" it is summedtogether' with the tens output portion of ROM -ALj, :60 or'cornbin'ational logic element). Simiflarlyethef hundreds portion of the data is taken from I {ROM el 'm'entsf50, and 7 0 a nd added together in Binary adder 210 fand'BCD adder 220 as is shown in F IG.

1. The thousands portion of outpu'tdata from element g 50 is inserted irito binaryadder 250; v

Adders 120, 2l0' ajndf'250 arebinary adders, such were used where the output would not exceed the capa- 1 i b ilityofa binary adderi where the capability might be exceeded, BCD adders were used. The binary adders,

' as well as the BCD adders used are well known in the art; The binary adders used are produced by Texas lnstruments Inc. -(Tll) having part number Ser. No. 7,483

range.-

as well as the first four entries for ROM 1 00 represent positive number input. When a number is negative, the w second half of thetable entries are'acces'sedi When a negative number is used, what is being-converted is a onescomplement number. In actual fact, atwos complement number is desired for the negative number.

From the truth table, it is seen'that the negative number is treated as a ones complement up to the input of each 1 ROM element. On the negative portion of the table, a

least significant binarybit is added in the digital or decimal domain. Thus the correction is made'directly in the table entry.

Binary coded decimal (BCD) to Binary (BlNlcon: verter 4, is shown inFlG. 2 and operates on the same basic principles provided for converter 2 Conversion tured by lntersil Corp. having an EA! part No.

' In general as has been described, fractional outputs 592.0279-0. In ROMs 300 and 310, the input applied is the thousands portion of the BCD number which is being converted. Fiveaddress lines are connected to ROMs 300, 310 representing 8000, 4000, 2000, 1000 and the sign bit. Elements 320, 330 accept the hundreds portion of the BCD number, elements 340 and 350 accept the tens portion and finally element 360 accepts the units portion of the number. Note that element 340 mayeither be a ROM element or a logic block for conversion. Each logic element is hard wired As an example to show the flow of information programmed to produce binar least significant four bits from element 360 and 35 vide the appropriate conver the 0 are y datum. ln order to prosion elements 300, 310, summed together in adder pack 400. This summation programmed in accoris applied to adder pack 440 where it is added to the ance with the following truth tables: 5 least significant four bits from element 330. The total 320, 330, 340, 350 and 360 are d TRUTH TABLE BCDTOBINCONVERTER4 '5 300,3)

HUNDREDS ROMs 320,330 ADDR. OUTlN HEX THOUSANDSROM ADDR. OUT IN HEX 8421 SlGNHHHH 8421 SIGN K K K K UPPER UPPER LOWER LOWER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 0000 0000 0000 10000 00000000 l l 1 l 1 00000000 1 l l 1 1 l 1] 0000000000000000 l 1 1 l l 1 1 1 1 1 l l 1 1 11 UNITS ROMs 360 ADDR. OUTlN HEX TENS ROM"s 340.350 ADDR. OUT IN HEX LOWER 8421 LOWER SIGN U U U U UPPER 8421 SlGNTTTT UPPER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 0000 0000 0000 0000 00000000 l 1 1 l l l 00000000 1 l l 1 l l 1] 0000000000000000 1 1 l 1 l 1 1 l 11 from summer 440 is applied to adder 480 where it is summed with the least significant four bits from element 310. The output from adder 480 is then buffer unit 540 prior to read out. Similarl The binary output of the hard wired logic elements 65 are summed together in adder packs 370 through 480 as shown in FIG. 2. The adder packs are standard biplaced in y, the next nary adders, one type which was used being manufactured by Texas Instruments Inc. having a part number four bits are taken from elements 360 and 350, applied Ser. No. 7,483.

to adder 390 and pass through adder stages 430, 470

spectively'to be added to the last adder pack total. The output is then placed in buffer unit 530.The next four pic king up information from elements 330 and 310 rebits pass from adders 380, applied to element 420, and 1' I adder 460 to be finally inserted into buffer unit 520.

' Summer packs 370, 410, and 450 operate on bits 1, 2, 3 and 4m a manner similar to that described, and input such into buffer 510prior to read out.

As an example assume that the number +0.937l is to ,be converted from BCDto binary-code. In BCD format,-the coefficient of 0.9371 are represented by .01001, 00011, 00111, 00001. Where the most signifi-' ,cant bit in each group of 5 represents the sign, thein general, as has been described, the codefconvertei' system permits utilization of an inputas an address in the table lookup of a different number system. If the code conversion were done on a 1:1 basis, such a scheme would require on the order of 20,000 lookups.

' Sirr'iilarly, where two tables are used, then v200 lookups are required. In the present-system, four conversion tables are'provided which require only 20 lookups. Thus,

bydividirig the code into word segments contained in individual tables, and adding different segments together, a capability of 20,000lookups is achieved.

least five bits are operated upon in ROM element 360.

- The decimal number is +0.0001 which has a fractional binary equivalent of 0000, 0000, 0000, 01 1 l.-The next five bitsin BCD ,fo'rmat are-00111 which represent the digit of the decimal number +0.007. These four bits are operated upon in ROM element 360. The resulting Y fractional binary equivalent is 0000, 0001, 1 100, 101 l.

At this point two word' segments in fractional binary have been formed and these word segments are arith metically added together as has been described. The outputs of adder elements 370, 380, 390 and 400 now contain the fractional binary equivalent of 0.0071

, which is 0000 0001 1101 0010.

The next BCD character 00011 is operated upon in v ROMs 320 {and 330. This corresponds to the decimal number +0.03 (of the original decimal number 09371). The .-1-0.03breaks down to the 1-6 bit fractional'binary word 000 01 l 1 1010 1 1 10 which is added to the previous sum 0.0071 (0000 0001 1101 0010) in adders 410, 420, 430'and 440. At the output of these adders, the word appears as-0000 1001 1000 0000.

Finally, the BCD character 01001 (representing +0.9) is operated upon by ROMs 300 and 310. The

I, fractional binary is 1 l 10 01 10 01 10 01 10. This output is added to the previous total in adder elements 450,

A V 460, 470 and 48 0 to achieve the final result 1 110 1111 40 What is claimed is: e

'1. A system for converting digital input signals to digital output signalsbetween binary coded decimal and binary code signals, comprising:

a. hard wired logic means having a programmed m apping between said codes, said logic means having said'input signal applied in one of 'said codes and for producing a signal in the other of said codes,

said logic means including aplurality of read only memory means connected each to the other in par-' allel fashion, each of said read only memory means having a predetermined decade-of information applied thereto in said input signalcode;

b. storage register means for holdingpredetermined decades of information signals, said storage register 7 

1. A system for converting digital input signals to digital output signals between binary coded decimal and binary code signals, comprising: a. hard wired logic means having a programmed mapping between said codes, said logic means having said input signal applied in one of said codes and for producing a signal in the other of said codes, said logic means including a plurality of read only memory means connected each to the other in parallel fashion, each of said read only memory means having a predetermined decade of information applied thereto in said input signal code; b. storage register means for holding predetermined decades of information signals, said storage register means applying said signals to said read only memory means, at least one of said storage register means applying an information signal to each of said read only memory means for determining the sign of a number being applied to said read only memory means in said input signal code; and c. summing means connected to said logic means for summing said signals from said logic means for producing said digital output signal in one of said codes. 